As the conventional MOSFET device is continuously downsized in proportion, the source/drain resistance is not proportionally reduced along with the decrease of the channel size, and particularly, the contact resistance is increased approximately by being squared along with the size decrease, thus the equivalent working voltage is decreased, and the properties of the device downsized in proportion are greatly influenced. In the prior art for manufacturing an MOSFET, if the conventional highly doped source/drain is replaced by a metal silicide source/drain, the parasitic series resistance and the contact resistance can be significantly reduced.
FIG. 1 is a schematic view of the existing metal silicide source/drain MOSFET (also referred to as Schottky barrier source/drain MOSFET). Metal silicide source/drain regions 3A and 3B are formed on the two sides of a channel region 2A or 2B in a bulk silicon substrate 1A or a Silicon-On-Insulator (SOI) substrate 1B. A gate structure 4A/4B and a gate sidewall spacer 5A/5B are successively formed in the channel region. In which, the metal silicide is completely used as the source/drain material that directly contacts the channel, without the conventional ion implantation procedure for forming a highly doped source/drain. The device substrate may be further provided with a Shallow Trench Isolation (STI) 6A/6B. In FIG. 1, the STI is just shown for the convenience of illustration, rather than being directly interposed between the bulk silicon substrate and the SOI substrate, and those two substrates actually are not connected to each other.
In the Schottky barrier source/drain MOSFET, the driving capability of the device depends on the Schottky Barrier Height (SBH) between the metal silicide source/drain region 3A/3B and the channel region 2A/2B. The driving current is increased when the SBH is reduced. The device simulation is result shows that when the SBH is reduced to about 0.1 eV, the metal silicide source/drain MOSFET can achieve a driving capability the same as that of the conventional large-size highly doped source/drain MOSFET.
The metal silicide is usually Nickel-based metal silicide, such as NiSi, NiPtSi and NiPtCoSi generated through a reaction between Si in the substrate channel region and Ni, NiPt and NiPtCo. Regarding the contact between the Nickel-based metal silicide and the silicon, the SBH (or marked as Φb) is usually relatively large, such as 0.7 eV. Thus the device has a relatively small driving current, which restricts the application of the new MOSFET that reduces the source/drain resistance through the Nickel-based metal silicide. Therefore, it requires a new device capable of effectively reducing the SBH between the source/drain of the Nickel-based metal silicide and the silicon channel, and a method for manufacturing the same.
FIGS. 2A to 2D are cross-section views of the steps of a method for reducing the SBH between the Nickel-based metal silicide and the silicon by taking the metal silicide as a doped source (SADS). In which, firstly as illustrated in FIG. 2A, a gate stacked structure 4A comprising a gate insulation layer 41 and a gate conduction layer 42 is formed on the substrate 1, and gate sidewall spacers 5A are formed on both sides of the gate stacked structure 4A. Next, as illustrated in FIG. 2B, a Nickel-based metal layer is deposited on the device, usually comprising Ni, NiPt, NiCo, NiTi or a ternary alloy thereof. Then a one-step SALICIDE process (annealing at about 500□ to form a low resistance phase of the Nickel-based metal silicide) or a two-step SALICIDE process (firstly annealing at about 300□ to form a Ni-rich phase, and secondarily annealing at about 500□ after the unreacted metal is removed, to form a low resistance phase of the Nickel-based metal silicide) is performed, so as to consume Si of a part of the substrate 1 and form a source/drain region 3A of the Nickel-based metal silicide therein. Particularly, the current SALICIDE process preferably uses the two-step is annealing method. Next, as illustrated in FIG. 2C, ions are implanted into the source/drain region 3A of the Nickel-based metal silicide, i.e., p-type impurity ions such as boron (B) are implanted for pMOS, while n-type impurity ions such as arsenic (As) are implanted for nMOS. Finally as illustrated in FIG. 2D, a drive annealing is performed, and the implanted ions are gathered and condensed at the interface between the source/drain region 3A and the channel region of the substrate 1 under the driving of the drive annealing (e.g., about 450˜850□) to form a condensation region 7 of the impurity ions, thereby effectively reducing the SBH and improving the driving capability of the device.
However, the above method that reduces the SBH using the SADS still has the following deficiency: impurity ions implanted into the source/drain region 3A of the Nickel-based metal silicide have a poor solubility, and large quantity of the implanted ions cannot be solid-soluble in the Nickel-based metal silicide, thus the number of the impurity ions available for reducing the SBH is not enough. By means of grain boundary diffusion, the implanted ions are segregated by grain-boundary diffusion at the interface between the Nickel-based metal silicide and the silicon to form the condensation region 7. But the temperature of the driving annealing is low and is not sufficient to completely activate the segregated impurities, thus the effect on reducing SBH is not significant. Therefore, the above conventional method is not enough to reduce the SBH to a level below 0.1 eV.
In summary, the existing MOSFET cannot effectively reduce the SBH, and then cannot effectively decrease the source/drain resistance and meanwhile effectively improve the driving capability of the device. Thus the electric properties of the semiconductor device are seriously influenced, and it emergently requires a semiconductor device capable of effectively reducing the SBH and a method for manufacturing the same.